File Name: tep by tep functional verification withy temverilog and ovm .zip
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With many examples and clear descriptions, it should be helpful to anyone involved in IC functional verification. Iman brings together all the essential elements to understand the use and application of OVM. This book has everything design and verification engineers would want to know to apply OVM to their most pressing challenges.
Sasan Iman SiMantis Inc. Suite Santa Clara, CA iman simantls. This work may not be translated or copied in whole or in part without the written permis- sion of the publisher Hansen Brown Publishing Company, info hansenbrown. Use In connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to pro- prietary rights. By now, the metaphor of "the perfect storm" is in danger of becoming a cliche to describe the forces causing rapid evolution in some aspect of the electronics industry.
Nevertheless, the term is entirely applicable to the current evolution-arguably even a revolution-in func- tional verification for chip designs.
Three converging forces are at work today: complexity, language, and methodology. The challenges posed in the verification oftoday's large, complex chips is well known.
Far too many chips do not ship on first silicon due to functional bugs that should have been caught before tapeout. Hand-written simulation tests are being almost entirely replaced by constrained-random verification environments using functional coverage metrics to deter- mine when to tape out.
Specification of assertions, constraints, and coverage points has become an essential part of the development process.
The SystemVerilog language has been a major driver in the adoption of these advanced verification techniques. SystemVerilog provides constructs for assertions, constraints, and coverage along with powerful object-oriented capabilities that foster reusable testbenches and verification components. The broad vendor support and wide industry adoption of Sys- tem Veri log have directly led to mainstream use of constrained-random, coverage-driven ver- ification environments.
However, a language alone cannot guarantee successful verification. SystemVerilog is a huge language with many ways to accomplish similar tasks, and it doesn't directly address such essential areas as verification planning, common testbench building blocks, and com- munication between verification components.
Such topics require a comprehensive verifica- tion methodology to tie together the advanced techniques and the features of the language in a systematic approach. The OVM leverages many years of verification experience from many of the world's experts. It was greeted with enormous enthusiasm by the industry and is used today on countless chip projects. Thus, the timing of this book could not be better. It provides thorough coverage of all three forces at work.
The complexity challenge is addressed by timely advice on verification planning and coherent descriptions of advanced verification techniques. Many aspects of the SystemVerilog language, including its assertion and testbench constructs, are covered in detail. Finally, this book embraces the OVM as the guide for verification success, providing a real-world example deploying this methodology. Functional verification has never been easy, but it has become an overwhelming prob- lem for many chip development teams.
This book should be a great comfort for both design and verification engineers. So grab a beverage of your choice and curl up in a com- fortable chair to learn how to get started on your toughest verification problems. Part 1: Verification Methodologies, Planning, and Architecture. Black-Box Assertions Chapter 5: SystemVeriiog as a Verification Language Coverage Collection Part 3: Open Verification Methodology Part 5: Environment Implementation and Scenario Generation.
Part 6: Assertion-Based Verification Current Value Functional verification has been a major focus of product development for more than a decade now. This period has witnessed the introduction of new tools, methodologies, lan- guages, planning approaches, and management philosophies, all sharply focused on address- ing this very visible, and increasingly difficult, aspect of product development. Significant progress has been made during this period, culminating, in recent years, in the emergence and maturity of best-in-class tools and practices.
These maturing technologies not only allow the functional verification challenge to be addressed today, but also provide a foundation on which much-needed future innovations will be based.
This means that having a deep under- standing of, and hands-on skills in applying, these maturing technologies is mandatory for all engineers and technologists whose task is to address the current and future functional verifi- cation challenges. A hallmark of maturing technologies is the emergence of multi-vendor supported and standardized verification languages and libraries. SystemVerilog is an extension of Verilog IEEE Standard , and enhances features of Verilog by introducing new data types, constrained randomization, object-oriented programming, assertion constructs, and coverage constructs.
OVM, in tum, provides the methodology and the class library that enable the implementation of a verifica- tion environment according to best-in-class verification practices. This book is intended for a wide range of readers. It can be used to learn functional ver- ification methodology, the SystemVerilog language, and the OVM class library and its meth- odology.
This book can also be used as a step-by-step guide for implementing a verification environment. In addition, the source code for the full implementation of the XBar verifica- tion environment can be used as a template for starting a new project. As such, this book can be used by engineers starting to learn the SystemVerilog language concepts and syntax, as well as advanced readers looking to achieve better verification quality in their next verifica- tion project.
Acknowledgements The creation of this book would not have been possible without the generous support of many individuals. I am especially grateful to David Tokic and Luis Morales for helping tum this book from a nascent idea into a viable target, to Susan Peterson for getting this project off the ground and for her infectious positive energy, and to Tom Anderson for his continued technical and logistical guidance and support throughout the life of this effort.
Special thanks also go to Sarah Cooper Lundell and Adam Sherer for valuable planning and technical dis- cussions, and to Ben Kauffman, the technical editor. I would like to thank Cadence Design Systems and the Verification Alliance program for their generous support of this effort.
The technical content of this book has benefited greatly from feedback by great engi- neers and technologists. Special thanks go to David Pena and Zeev Kirshenbaum for itt-depth discussions on many parts of this book.
In addition, technical feedback and discus- sions by individuals from a diverse set of companies have contributed significantly to improving the technical content of this book. I am especially grateful to these individuals whose nan:les and affiliations are listed below.
Sasan Iman Santa Clara. CA Spring Feedback We welcome your feedback on this book. Please email your feedback to: fvsvovm simantis. This book provides a complete guide and reference for functional verification methodology, learning the System Verilog language, and for building a verification environment using Sys- temVerilog and the OVM class library. Given the range of material covered in this book, it is expected that the focus of anyone reader may be on one specific topic, or that anyone reader may prefer to bypass familiar content.
To better support the range of readers who can benefit from this book, its content is grouped into parts. These parts are ordered so that the prerequi- site knowledge required for any topic is covered in the parts appearing before that topic.
This means that this book can be studied in a linear fashion, but the clear breakdown of topics into these parts facilitates selective focus on anyone topic. This part also provides a detailed description of verification planning for a cov- erage-driven verification flow chapter 2. The architectural view of a verification environment is also described in this part of the book chapter 3.
The discussion in this part of the book is implementation independent, and pro- vides the background that is necessary before a verification solution can be imple- mented.
This part can be used to learn the syntax and semantics of the SystemVerilog language, and to also learn its veri fication related features.
In addition to chapter 4, randomization features are described in chapter 10, assertion features are described in chapter 15, and coverage features are described in chapter The content in this part is organized through tables and examples so it can also be used as a desk reference for the SystemVerilog language.
Chapter 9 describes transaction and channel interfaces, and their implementation using the predefined classes of the OVM class library.
The discussions in this part describe the architectural view of verification environ- ment elements based on OVM constructs, and illustrate the implementation of these elements through small and self-contained examples. The use of OVM con- structs described in this part of the book for implementing a full-scale verification environment is described in part 5 of this book.
ThIs part also describes techniques and the relevant issues for building a data model using the SystemVerilog language constructs chapter It also describes the implementation of transaction sequences for modeling verification scenarios chapter The description in this part is based on the XBar design, a cross-bar switch section The discussions on class-based implementation of the verifi- cation environment for the Xbar design chapter 13 and the generation of its trans- action sequences chapter 14 provide a complete example of a verification environment implementation using the OVM class library and its recommended guidelines.
A good understanding of the material in this part is needed for having the ability to write concise and complex properties, and to make effective use of assertions in reaching verification closure. The definition of a coverage plan, implementa- tion of a coverage plan using the constructs provided by SystemVerilog, and the flow for carrying out a coverage-driven verification flow is described chapter The introduction of SystemVerilog as a new hardware design and verification language is motivated by the need for a powerful tool that can facilitate the implementation of the latest verification methodologies.
As such, having intimate knowledge of the challenge posed by functional verification, the latest verification methodologies, and the way in which design and verification flow fit together is a first step in the successful use of SystemVerilog in completing a verification project.
This chapter brings functional verification into focus by describing its context, the chal- lenges it raises, and the approaches that best address these challenges. Section 1. The execution of a verification project cannot be improved without tangible metrics for evaluating its quality.
Finally, section 1. A functional verification project plays against the backdrop of a product development flow. The following subsections describe the product design flow, the meaning of functional verifi- cation and challenges that must be met to successfully and efficiently execute a verification project.
This knowledge is also necessary for understanding the effect of local verification decisions on the overall progress and effectiveness of verification. This section provides an overview of the design flow. Descriptive Tex! Product development flows are as varied as the products they produce.
Most flows, however, can be described in terms of abstract phases corresponding to product idea devel- opment and design and implementation stages. Figure l. A product is usually scoped by a marketing team as an opportunity to satisfy a demand in the marketplace. The initial description of a product must be described with careful consideration of the overall abilities and limitations of the underlying technologies.
This consideration is essential for delivering the product with good confidence, on target, and with the desired functionality. The initial product intent is turned into a functional description through discussions between the marketing team and product and system engineers.
Sasan Iman SiMantis Inc. Suite Santa Clara, CA iman simantls. This work may not be translated or copied in whole or in part without the written permis- sion of the publisher Hansen Brown Publishing Company, info hansenbrown. Use In connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to pro- prietary rights. By now, the metaphor of "the perfect storm" is in danger of becoming a cliche to describe the forces causing rapid evolution in some aspect of the electronics industry.
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Skip to Main Content. A not-for-profit organization, IEEE is the world's largest technical professional organization dedicated to advancing technology for the benefit of humanity. Use of this web site signifies your agreement to the terms and conditions. Using class libraries with SystemVerilog can take this a step further by enhancing productivity, and enabling better, more efficient reuse between engineers and between projects. The verification methodology manual VMM class library was one of the first SystemVerilog class libraries available, and has been widely adopted.
Functional verification is an art as much as a science.
All rights reserved. IDesignSpec is an engineering application that transforms a functional specification of registers in a digital system into code. These designs typically have one or more microcontrollers or microprocessors along with severa.
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